In order to realize reduction in size and thickness as well as enhancement of functionality of electronic devices such as a computer, a communication device and a display device, various miniaturized and highly-integrated semiconductor chips (IC), for example, LSI chips such as a microprocessor are used. These semiconductor chips include ones which consume large current.
The semiconductor chip is loaded and mounted on a substrate called, for example, a package substrate or an interposer (intermediate) substrate, which is loaded on a system board (a system substrate, a motherboard) to be part of an electronic circuit in an electronic device.
The semiconductor chip is flip-chip mounted on the package substrate by bump electrodes arranged on a bottom surface in an array state, and the package substrate is loaded on the system board by, for example, a BGA (Ball Grid Array) and so on.
As the package substrate, a multilayer wiring substrate is used, in which conductive layers such as a signal wiring pattern layer, a power supply layer and a ground layer are stacked through interlayer insulating layers and the conductive layers are connected to one another by vias, through holes and so on which are formed so as to pierce through the interlayer insulating layers. The multilayer wiring substrate is fabricated by using, for example, a build-up method. The power supply layer and the ground layer of the package substrate are generally connected to upper and lower conductive layers by a large number of vias for improving electric characteristics such as loop inductance.
As a related-art documents concerning the multilayer wiring substrate to which electronic parts are loaded, for example, there is JP-A-2007-221014 (Paragraph 0008 to 0015, FIG. 1, FIG. 2) (Patent Document 1) entitled “Multilayer wiring substrate structure”, which wrote the following description.
As the major characteristics of the technology in Patent Document 1, a plurality of reinforcement vias to be current flow paths are formed around a through hole in which large current flows, and one or plural conductive patterns electrically connecting the through hole to the reinforcement vias are formed at a substrate outer layer and a substrate inner layer, thereby distributing current to surrounding reinforcement vias so that current is not concentrated only in the through hole, and at the same time, the through hole can be heated to a temperature sufficient for melting solder in a process of soldering an electrode terminal to the through hole.
When current flows in one or a small number of through holes in a concentrated manner, heat is generated at a connecting portion between the through hole and the power supply layer. However, the addition of the reinforcement vias disperses generated heat in the through hole and the reinforcement vias as current flows in a dispersed manner, which suppresses temperature increase.